Embodiments of the present specification relate to electronic packages, and more particularly to electronic packages having pre-defined via patterns.
Technological advancements in the area of electronic devices have experienced vast growth in recent years. For example, while cellular phones are becoming smaller and lighter, their features and capabilities are simultaneously expanding. This has caused an increase in the complexity and operation of the electrical components found in such devices and a decrease in the amount of space available for such components. Several challenges arise from such an increase in the complexity of the electrical components and decrease in the amount of space available. For example, based on space limitations, circuit boards are reduced in size to an extent that the routing density for the board may be constrained and limited below a desired amount. As integrated circuits (ICs) become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging to laminate-based ball grid array (BGA) packaging and eventually to chip scale packaging (CSP). Advancements in IC chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
Furthermore, due to the small size and complexity of IC packages, the process for fabricating the IC packages is typically expensive and time consuming. Also, use of additional re-distribution layers to create desired double-sided input/output (I/O) systems increases the number of processing steps, further increasing the cost and complexity of the manufacturing process. Moreover, increasing I/O per device increases routing density and number of vias that are required per device.